A conventional method used by the semiconductor industry in the manufacturing of semiconductor integrated circuits includes the steps of fabrication, wafer sort, assembly and test, respectively. As shown in FIG. 1, in the fabrication step, as many as several thousand dies (integrated circuits) 5 are formed onto a semiconductor wafer 4. In the wafer sort step, each of the dies 5 on the wafer 4 is tested to determine its electrical characteristics and operability, and defective dies are distinguished from operable dies. The defective dies are often marked by an ink mark at the wafer sorting step. In the assembly step, the unmarked, operable dies are assembled into a package, and in the test step, the packaged integrated circuits are tested for operability and reliability.
At the wafer sort step, the dies are tested to establish which dies on the wafer function properly. Each die is tested to all functional product specifications for both DC and AC parameters. Four testing objectives are pursued: (1) chip functionality, in which all chip functions are tested to ensure that only fully-functional chips are assembled and packaged in subsequent steps; (2) chip sorting, in which chips are separated or sorted on the basis of their operating speed performance under various voltage and timing conditions; (3) fab yield response, which yields important information that may lead to improvements in the overall fabrication process; and (4) test coverage, in which high test coverage of the internal device nodes is achieved at the lowest possible cost. The wafer sort procedure is similar to the in-line parametric test except that every die on the wafer is tested, in many cases using the same automated test equipment (ATE). Furthermore, the wafer sort procedure is usually located in a separate facility under less stringent purity conditions than those in which the parametric test is carried out, since wafer fabrication is essentially complete.
In automated wafer handling during wafer sort, a correlation wafer is used to verify tester setup. The correlation wafer is a control wafer the functionality of which has been verified and ensures that the testing system is working properly. After indexing from the cassette to the prober, the wafers are mounted on a vacuum chuck with Z (vertical) positioning. Using software, mechanical probe needles are aligned and contacted with bond pads on the wafer to establish electrical communication between the testing equipment and the dies on the wafer. The probes are interfaced with the ATE to perform the range of AC functional tests based on test algorithms. The type, number and order of tests are defined by the test program.
After testing, die found to be defective are labeled in a computer database to exclude the die from subsequent packaging steps. The labeling method is typically performed by placing a drop of ink on each unacceptable die. Because the ink marking process can be messy and introduce possible contaminants onto the chip, electronic wafer maps are increasingly being used to create a computer image of chip location and test results to categorize good and bad die on the wafer. At the chip assembly stations, the electronic wafer maps are downloaded into an equipment database to ensure that defective chips will not be packaged.
As further shown in FIG. 1, in an integrated circuit pattern of each dice 5, the input, output, power supply and other terminals of the circuit are formed by multiple metalized contact pads 6, adjacent ones of which are usually deployed in lines along the periphery or margins of the pattern in what is commonly known in the art as a test key pattern. Metal lines or traces 7 electrically connect the contact pads 6 to the circuit elements of the dice 5. The outline of the test key pattern is either square or rectangular, and the marginal locations of the contact pads thereon depend on the circuit configuration and the available marginal space. Thus, in a relatively simple circuit pattern, all of the marginal space may be available for contact pads, whereas in more complex circuits, portions of the circuit may invade the marginal areas so that contact pad placement is restricted to the free marginal areas. In some instances, therefore, the contact pads may lie in more or less uniform rows along the margins, and in other cases, the contact pads may be randomly spaced from each other.
Immediately following manufacture of the IC, the electrical characteristics of the device must be tested using a test probe assembly which includes a test probe card consisting of a printed circuit board having an opening therein to provide access to an IC pattern. The opening is surrounded by a ring of conductive pads connected by the printed circuit card to terminals for connection to test equipment appropriate for testing the circuit. The number of pads in the ring determines the maximum capacity of the probe card.
A higher degree of integration in recent semiconductor devices has led to an increase in the number of electrodes in ICs and to a decrease in the size of the electrode pads which are contacted by the probe needles. The reduction in size and increase in density of the probe needles has inevitably made the manufacture and mounting of the needles on the probe card troublesome. The tips of the probe needles are ideally all disposed at the same height level and same angle, but these and other parameters of the needles fluctuate somewhat for a number of reasons. These variations in probe needle parameters reduce test precision and reliability.
The effectiveness, reliability and repeatability of IC testing using a probe card depends on a number of factors and characteristics of the probe card, and particularly the probe needles, including size, alignment, leakage, contact resistance and the force applied by the needles. For this reason, each probe card is usually designed for a particular test key pattern on a wafer having a specific pitch and number of contact pads to be tested, and each probe card is typically incompatible with other test key patterns. Consequently, fabrication of chips having various test key patterns requires that a probe card that matches each test key pattern be designed and manufactured to fit that pattern before those chips can tested. This probe card design and manufacture process is inconvenient and may introduce a delay of up to several weeks into the chip fabrication process. Accordingly, an automatically adjustable wafer probe card is needed which is capable of automatically adjusting to the characteristics of a particular test key pattern on a chip, including the number, pitch and height of the probe needles on the probe card.
Accordingly, an object of the present invention is to provide a probe card which is capable of accommodating dies having a variety of test key patterns.
Another object of the present invention is to provide a probe card having multiple probe needles the number of which may be selected for a particular application depending upon the number of contact pads to be tested on an integrated circuit.
Still another object of the present invention is to provide a probe card having multiple probe needles, the pitch of which may be automatically adjusted depending on the test key pattern or contact pad spacing or configuration on an integrated circuit.
Yet another object of the present invention is to provide a probe card having multiple probe needles, the height of which may be automatically adjusted for a particular application.
A still further object of the present invention is to provide a probe card which prevents the need to fabricate multiple test cards for the testing of integrated circuits having various test key layouts.
Another object of the present invention is to provide an automatically adjustable wafer probe card which includes multiple probe needles that are mounted for linear adjustment along a pitch shift track to facilitate selection of a desired number of probe needles as well as the pitch, or spacing between probe needles, for the testing of integrated circuits fabricated on a wafer.